1. Field of the Invention
The invention relates generally to a flash EEPROM cell and method of manufacturing the same. More particularly, the present invention relates to a flash EEPROM cell in which two floating gates having different sizes can be simply formed at a single cell using a hard mask layer in a multi-level cell, capable of preventing lower of the quality of a tunnel oxide film and increasing the coupling ratio, and method of manufacturing the same.
2. Description of the Prior Art
The greatest bottleneck to prevent customization of the current flash EEPROM is that the cost per unit information is high. For this, the higher integration of a cell is required and thus various manufacturers have made an effort to develop it. However, as the structure of the EEPROM is complicated compared to that of the DRAM, there is a problem that the integration level of the EEPROM is difficult to increase.
The conventional flash EEPROM cell has only two states (storing only binary information) depending on whether the electrons is charged at the floating gate or not. Thus, it has a drawback that the chip size is increased due to one bit per one cell in the large-scale configuration of the cell array depending on it.
On the other hand, as the multi-level cell has four states, it can store information at one cell instead of storing it at two cells. Thus, it can store much information at the same area. However, in the multi-level cell, as two floating gates have to be formed at one cell, many processes has to be experienced to manufacture it. Also, as forming the tunnel oxide film has to be performed in two steps, it is difficult to assure the quality of the tunnel oxide film and to assure the quality of the tunnel oxide film below a poly spacer in case of using the poly spacer.
It is therefore an object of the present invention to provide a flash EEPROM cell in which two floating gates having different size can be simply formed at a single cell using a hard mask layer in a multi-level cell, capable of preventing lower of the quality of a tunnel oxide film and increasing the coupling ratio, and method of manufacturing the same.
In order to accomplish the above object, a flash EEPROM cell according to the present invention is characterized in that it comprises first and second floating gates, that are different in size and separated in two, formed to be electrically separated from a semiconductor substrate by a tunnel oxide film; control gate formed to be electrically separated from said first and second floating gates by a dielectric film; drain junction formed on said semiconductor substrate at the side of said first floating gate; and source junction formed on said semiconductor substrate at the side of said second floating gate.
Also, in order to accomplish the above object, the method of manufacturing a flash EEPROM cell according to the present invention is characterized in that it comprises the steps of sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substarate; patterning said hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the polysilicon layer for the floating gate by etching process using said patterned hard mask layer and said hard mask layer spacer as etching mask thus to form first and second paterns that are separated in two; removing said patterned hard mask layer and said hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a control gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process; and forming a drain junction and a source junction by cell source/drain ion implantation process.